This invention relates to a semiconductor memory device with banks, such as a synchronous dynamic random-access memory (hereinafter, referred to as a synchronous DRAM).
After the manufacture of semiconductor memory devices, the function of their memory cells are generally tested and only good products are shipped. In recent years, semiconductor memory devices have been stepped up in storage capacity and the time required to test memory cells has increased. In testing memory cells, all "1" data or all "0" data is written into the memory cell array. Then, the written data is read out to check whether the data has been written into each memory cell properly. Therefore, when a memory to be tested has a large storage capacity, the time required to write the data into or read out the data from the memory cells is long, leading to a decrease in the throughput.
For example, to carry out the test on a semiconductor memory device with banks, such as a synchronous DRAM, the data write operation is conducted for each bank. Specifically, in the case of, for example, a synchronous DRAM with two banks, a bank select signal is used to select a first and then second bank. With the first word lines of the first and second banks being activated, the column lines of the first bank are selected sequentially and the data is written into the memory cells selected by the first word lines and the column lines in the first bank. Then, the column lines of the second bank are selected sequentially and the data is written into the memory cells selected by the first word lines and column lines in the second bank. Thereafter, the second word lines of the first and second banks are selected sequentially and the above operation is repeated. By repeating the operation on subsequent word lines of the first and second banks, the data is written into all the memory cells in the first and second banks. For this reason, testing the memory takes a long time because the data have to be written into the memory cells in the above manner. Therefore, the larger the number of banks, the longer time the testing needs.
To overcome this drawback, the technique for shortening the testing time has been developed. For example, Jpn. Pat. Appln. KOKAI Publication No. 9-147551 disclosed a technique for shortening the testing time by selecting plural banks simultaneously in the test mode and writing the data into the selected plural banks simultaneously.
In the prior art, only ordinary memory cell arrays have been tested but the spare cells constituting the redundancy circuit have not been tested. Semiconductor memory devices generally have spare rows or spare columns. According to the result of testing only normal cell arrays, it is found that there are a defective row or column, the defective row or column is replaced with a spare row or column. If the spare row or column to be replaced has a defect, the defective row or column is replaced with the defective spare row or column, and thus the defect cannot be relieved, failing to improve the yield. Therefore, in large-capacity semiconductor memory devices, it is important to test the spare cells beforehand. In the prior-art semiconductor memory devices, however, the spare cells have not been tested.
Further, in a conventional technique for selecting plural banks simultaneously in the test mode and for writing the data into the selected plural banks simultaneously, it may be that, for example, a command to activate a bank will be lost and a certain bank be not activated. In the prior art, even when such an inactivated bank is present, the write driving circuit corresponding to the inactivated bank operates to write the data into the inactivated bank, which may lead to an increase in the drawn current.
It is, accordingly, an object of the present invention to overcome the disadvantages by providing a semiconductor memory device capable of not only testing the spare cells to improve the yield but also shortening the testing time by testing plural banks simultaneously with a smaller drawn current.